CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 45.
24. lappuse
... node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation , which distinguishes our approach from behavioral synthesis and complicates the problem . In the ...
... node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation , which distinguishes our approach from behavioral synthesis and complicates the problem . In the ...
32. lappuse
... nodes is processed . In order to execute an application based on hierarchical trees , the search algorithm begins at the root node to find the next visited nodes until it reaches a leaf . The root node is loaded in the PE Array and in ...
... nodes is processed . In order to execute an application based on hierarchical trees , the search algorithm begins at the root node to find the next visited nodes until it reaches a leaf . The root node is loaded in the PE Array and in ...
107. lappuse
... nodes , re- spectively . More importantly , the constraints ensure an optimal spill code placement [ 8 ] . The following merge - node constraints are added for all the merge nodes . * LOADK - jk50 Ve ; { eil ... ein } at ; { at jɩ ...
... nodes , re- spectively . More importantly , the constraints ensure an optimal spill code placement [ 8 ] . The following merge - node constraints are added for all the merge nodes . * LOADK - jk50 Ve ; { eil ... ein } at ; { at jɩ ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale