CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 3.
13. lappuse
... Multiplier Shifter IBUS Program Counter Shifter DMAU DBUS IBUS Instruction Memory Data Memory Figure 1 : Architecture Template The two - pipeline processor has two functional data paths . Both paths share the same register file , data ...
... Multiplier Shifter IBUS Program Counter Shifter DMAU DBUS IBUS Instruction Memory Data Memory Figure 1 : Architecture Template The two - pipeline processor has two functional data paths . Both paths share the same register file , data ...
31. lappuse
... multipliers , shifters ) and storage units ( RAM , register files ) . A configuration register stores its functionality and contains the operation - code and the control signals to define operation type and to select source and ...
... multipliers , shifters ) and storage units ( RAM , register files ) . A configuration register stores its functionality and contains the operation - code and the control signals to define operation type and to select source and ...
176. lappuse
... multiplier in each block is classified as Periodic or Mesochronous ( depending on the multi- plication factor ) . We refer the interested reader to [ 3 ] chapter 10 , where the fi ve classes of signal - clock synchronisation are ...
... multiplier in each block is classified as Periodic or Mesochronous ( depending on the multi- plication factor ) . We refer the interested reader to [ 3 ] chapter 10 , where the fi ve classes of signal - clock synchronisation are ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale