CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 28.
62. lappuse
... module . 4. A processor PR will communicate with a shared memory module SM , when some reader or writer of a queue Q ; is mapped onto PR and queue itself is mapped onto SM1 . 3.2 Performance Constraints 3.2.1 Bandwidth Constraint at ...
... module . 4. A processor PR will communicate with a shared memory module SM , when some reader or writer of a queue Q ; is mapped onto PR and queue itself is mapped onto SM1 . 3.2 Performance Constraints 3.2.1 Bandwidth Constraint at ...
84. lappuse
... Module has been created to instantiate all the necessary library objects and modules . The core of the P - UTOPIA application consists of three modules and 20 classes for a total of about 3000 SystemC - Plus source lines ( more than ...
... Module has been created to instantiate all the necessary library objects and modules . The core of the P - UTOPIA application consists of three modules and 20 classes for a total of about 3000 SystemC - Plus source lines ( more than ...
221. lappuse
... modules : feedback current flattening module called FCFM and the pipeline current flattening module called PCFM . The FCFM is responsible for measuring the instantaneous current consumption at the processor supply pin and generating two ...
... modules : feedback current flattening module called FCFM and the pipeline current flattening module called PCFM . The FCFM is responsible for measuring the instantaneous current consumption at the processor supply pin and generating two ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale