CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 16.
20. lappuse
... minimal paths through the data path ; these are the valid operations of the design . The procedure must be restricted to find " minimal " solutions , as there are generally an exponential number of solutions , scaling with the amount ...
... minimal paths through the data path ; these are the valid operations of the design . The procedure must be restricted to find " minimal " solutions , as there are generally an exponential number of solutions , scaling with the amount ...
111. lappuse
... minimal inter - arrival time . The period or min- imal inter - arrival time of a task T is denoted as P. All tasks are assumed to be independent - i.e . , they do not share resources or have any precedence relationships . An instance of ...
... minimal inter - arrival time . The period or min- imal inter - arrival time of a task T is denoted as P. All tasks are assumed to be independent - i.e . , they do not share resources or have any precedence relationships . An instance of ...
140. lappuse
... minimal impact on overall system energy consumption , but that such benefits are severely constrained by memory system bandwidth . This work presents a design space exploration of potential memory system architectures . A range of low ...
... minimal impact on overall system energy consumption , but that such benefits are severely constrained by memory system bandwidth . This work presents a design space exploration of potential memory system architectures . A range of low ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale