CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 80.
42. lappuse
... memory mapping in behavioral synthesis . We formalize the memory mapping as a set of constraints for the synthesis , and defined a Memory Con- straint Graph and an accessibility criterion to be used in the scheduling step . We present a ...
... memory mapping in behavioral synthesis . We formalize the memory mapping as a set of constraints for the synthesis , and defined a Memory Con- straint Graph and an accessibility criterion to be used in the scheduling step . We present a ...
43. lappuse
... memory table is created . This memory ta- ble is then completed by the designer who can select the variable implementation ( memory or register ) and place the variable in the memory hierarchy ( which bank ) . The result- ing table is ...
... memory table is created . This memory ta- ble is then completed by the designer who can select the variable implementation ( memory or register ) and place the variable in the memory hierarchy ( which bank ) . The result- ing table is ...
44. lappuse
... Memory table 2 MCG_2 a 0 0 b 0 2 C 0 1 tmp ( add2 ) mull Array of memory ! access 1 Array of memory a b c a c b access 2 Scheduling 1 Scheduling 2 [ add1 ) ( mull add2 ) 1 cs 2 cs_3 Data rate cs 4 criterion , but all the operations that ...
... Memory table 2 MCG_2 a 0 0 b 0 2 C 0 1 tmp ( add2 ) mull Array of memory ! access 1 Array of memory a b c a c b access 2 Scheduling 1 Scheduling 2 [ add1 ) ( mull add2 ) 1 cs 2 cs_3 Data rate cs 4 criterion , but all the operations that ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale