CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 31.
67. lappuse
... Machine ( OSM ) [ 11 ] . Previously this model has been applied successfully in modeling microarchitectures of processors . Our work shows that the same principle can be also applied to model the concurrency inherent in the OCA , thus ...
... Machine ( OSM ) [ 11 ] . Previously this model has been applied successfully in modeling microarchitectures of processors . Our work shows that the same principle can be also applied to model the concurrency inherent in the OCA , thus ...
70. lappuse
... machines are ordered according to their ages , or the durations since they become alive . With this scheme , an older state machine has higher priority to access resources than a younger state machine by default . However , if a ...
... machines are ordered according to their ages , or the durations since they become alive . With this scheme , an older state machine has higher priority to access resources than a younger state machine by default . However , if a ...
198. lappuse
... ( machine State [ j ] , op.OT [ i ] ) ; AddCycle ( macCycle , opcycle ) macCycle.Resources macCycle.Resources ; - = for each ro Є otcycle . ReadOperands path = AvailRP ( ro.Register , ro.Paths , macCycle ) ; macCycle.Resources = path ...
... ( machine State [ j ] , op.OT [ i ] ) ; AddCycle ( macCycle , opcycle ) macCycle.Resources macCycle.Resources ; - = for each ro Є otcycle . ReadOperands path = AvailRP ( ro.Register , ro.Paths , macCycle ) ; macCycle.Resources = path ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale