CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 10.
130. lappuse
... interval of length A. σ " ( A ) is the maximum number of processor cycles that may be avail- able to the stream within any time interval of length A. σ 3. IDENTIFYING DESIGN TRADEOFFS In this section we demonstrate one possible ...
... interval of length A. σ " ( A ) is the maximum number of processor cycles that may be avail- able to the stream within any time interval of length A. σ 3. IDENTIFYING DESIGN TRADEOFFS In this section we demonstrate one possible ...
165. lappuse
... interval T3 L T1 ( i + 1 ) T3 ( 1 ) | T1 ( +2 ) T3 ( i + 1 ) HW T20 T400 T2 ( i + 1 ) T4 ( i + 1 ) || SW 80us ... interval between initiations of two consecutive iterations [ 3 ] . The key idea of most HW / SW partition algorithms for ...
... interval T3 L T1 ( i + 1 ) T3 ( 1 ) | T1 ( +2 ) T3 ( i + 1 ) HW T20 T400 T2 ( i + 1 ) T4 ( i + 1 ) || SW 80us ... interval between initiations of two consecutive iterations [ 3 ] . The key idea of most HW / SW partition algorithms for ...
191. lappuse
... interval of lk . This schedule is constrained to the partial assignment , CFG . 5 : while 311,12 € L ; FusionGain ( 11 , 12 ) > a do 6 : 7 : Select the loop pair ( 11,12 ) with the highest fusion gain Fuse ( 11,12 ) and update FG 8 ...
... interval of lk . This schedule is constrained to the partial assignment , CFG . 5 : while 311,12 € L ; FusionGain ( 11 , 12 ) > a do 6 : 7 : Select the loop pair ( 11,12 ) with the highest fusion gain Fuse ( 11,12 ) and update FG 8 ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale