CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 51.
182. lappuse
... integrated in a single silicon die . In addition , a reduction in the time - to - market has led researchers to define methods based on the reuse of pre - designed , pre - verified modules in the form of intellectual properties ( IPs ) ...
... integrated in a single silicon die . In addition , a reduction in the time - to - market has led researchers to define methods based on the reuse of pre - designed , pre - verified modules in the form of intellectual properties ( IPs ) ...
206. lappuse
... integrated hardware / software solution . The integration technology used for building such MPSOCs from a set of hardware and software modules is typically based on low - level interfaces for the integration of the modules . For example ...
... integrated hardware / software solution . The integration technology used for building such MPSOCs from a set of hardware and software modules is typically based on low - level interfaces for the integration of the modules . For example ...
242. lappuse
... integrated into a single System - on - Chip ( SoC ) design . Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks . It therefore becomes ...
... integrated into a single System - on - Chip ( SoC ) design . Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks . It therefore becomes ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale