CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 86.
35. lappuse
... increase in the PE Array size does not mean an increase in data coherence but a decrease as shown by a higher ( PE . Table 2 shows these aspects for the third mapping solution . Table 2. Effects of PE Array and screen sizes on PE IPE ...
... increase in the PE Array size does not mean an increase in data coherence but a decrease as shown by a higher ( PE . Table 2 shows these aspects for the third mapping solution . Table 2. Effects of PE Array and screen sizes on PE IPE ...
234. lappuse
Figure 1 : Left : Increase in the total size of the objects allocated due to checksums . Right : Increase in the total heap space require- ments to run an application successfully . The curve shows the heap requirements of the original ...
Figure 1 : Left : Increase in the total size of the objects allocated due to checksums . Right : Increase in the total heap space require- ments to run an application successfully . The curve shows the heap requirements of the original ...
235. lappuse
... Increase over CSOBJ 4 % -X - auction calc firstaid jpeg pushpuzzle 0 % *** 22 * * 2 % -3 % 1000 10000 20000 Percentage Increase in Errors Missed ( compared to CSOBJ ) 50 % 45 % 40 % 35 % + -X - auction calc firstaid jpeg pushpuzzle 30 ...
... Increase over CSOBJ 4 % -X - auction calc firstaid jpeg pushpuzzle 0 % *** 22 * * 2 % -3 % 1000 10000 20000 Percentage Increase in Errors Missed ( compared to CSOBJ ) 50 % 45 % 40 % 35 % + -X - auction calc firstaid jpeg pushpuzzle 30 ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale