CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 47.
127. lappuse
... improvement by our SA formulation over the KLFM algorithm , while point WORSTDEV represents the best solutions computed by the KLFM algorithm . Similarly , Fig- ure 8 , Figure 9 , Figure 10 represent the data for graphs with 50 vertices ...
... improvement by our SA formulation over the KLFM algorithm , while point WORSTDEV represents the best solutions computed by the KLFM algorithm . Similarly , Fig- ure 8 , Figure 9 , Figure 10 represent the data for graphs with 50 vertices ...
143. lappuse
... improvement . The overall analysis here is best pre- sented by Figure 2 , which depicts the percent of L2 misses at various L2 sizes for each of a number of application data streams . The shift from metadata to knowledge base data ( SMD ...
... improvement . The overall analysis here is best pre- sented by Figure 2 , which depicts the percent of L2 misses at various L2 sizes for each of a number of application data streams . The shift from metadata to knowledge base data ( SMD ...
253. lappuse
... Improvement # of arch Improvement # of arch Improvement # of arch Improvement # of arch Improvement ( c ) Systreml Figure 8. Performance variation of 5 example systems during the exploration according to the number of buses . In each ...
... Improvement # of arch Improvement # of arch Improvement # of arch Improvement # of arch Improvement ( c ) Systreml Figure 8. Performance variation of 5 example systems during the exploration according to the number of buses . In each ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale