CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 72.
97. lappuse
... improve the quality of specification before implementation verification . 6. CONCLUSIONS AND FUTURE WORK In this paper , we proposed a verification process for SoC based on specification using UML and CWL . UML is used for modeling the ...
... improve the quality of specification before implementation verification . 6. CONCLUSIONS AND FUTURE WORK In this paper , we proposed a verification process for SoC based on specification using UML and CWL . UML is used for modeling the ...
116. lappuse
... improve performance , but such partitioning can also improve power consumption by performing computations more effectively and by allowing for longer microprocessor shutdown periods [ 11 ] . Dynamic Reconfiguration has emerged as a ...
... improve performance , but such partitioning can also improve power consumption by performing computations more effectively and by allowing for longer microprocessor shutdown periods [ 11 ] . Dynamic Reconfiguration has emerged as a ...
125. lappuse
... improve execution time slightly but consume an additional large amount of HW area . This is based on a similar reasoning of en- abling the cost function to explore more combinatorial possibilities . ( c ) we reduce weightage on some ...
... improve execution time slightly but consume an additional large amount of HW area . This is based on a similar reasoning of en- abling the cost function to explore more combinatorial possibilities . ( c ) we reduce weightage on some ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale