CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 91.
24. lappuse
Hardware Synthesis From Coarse - Grained Dataflow Specification For Fast HW / SW Cosynthesis Hyunuk Jung and Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul 151-744 , Korea { jung , sha}@ ...
Hardware Synthesis From Coarse - Grained Dataflow Specification For Fast HW / SW Cosynthesis Hyunuk Jung and Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul 151-744 , Korea { jung , sha}@ ...
25. lappuse
... hardware synthesis step , which is highlighted in Figure 2 , aiming to accelerate the hardware design and verification loop . Since the invocation order , or schedule , of dataflow nodes and the required hardware resources are given ...
... hardware synthesis step , which is highlighted in Figure 2 , aiming to accelerate the hardware design and verification loop . Since the invocation order , or schedule , of dataflow nodes and the required hardware resources are given ...
218. lappuse
... hardware . This technique is important in embedded cryptosystems since power analysis attacks ( that make use of the current variation dependency on data and program ) compromise the security of the system . The technique flattens the ...
... hardware . This technique is important in embedded cryptosystems since power analysis attacks ( that make use of the current variation dependency on data and program ) compromise the security of the system . The technique flattens the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale