CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 57.
185. lappuse
... Exploration Framework Figure 8 shows the framework for exploration of the space of possible mappings in mesh - based NoC architectures . It comprises Ips / cores portfolio Computation Task Graph Assign / Schedule ASIC 14 Architectural ...
... Exploration Framework Figure 8 shows the framework for exploration of the space of possible mappings in mesh - based NoC architectures . It comprises Ips / cores portfolio Computation Task Graph Assign / Schedule ASIC 14 Architectural ...
242. lappuse
... exploration . In this paper , we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of a case study involving an AMBA 2.0 based SoC subsystem ...
... exploration . In this paper , we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of a case study involving an AMBA 2.0 based SoC subsystem ...
251. lappuse
... exploration on these parameters remains as a future work . 5. EXPLORATION ALGORITHM Figure 5 describes the main procedure of the proposed technique : Select_Architecture . This procedure requires three inputs : the initial architecture ...
... exploration on these parameters remains as a future work . 5. EXPLORATION ALGORITHM Figure 5 describes the main procedure of the proposed technique : Select_Architecture . This procedure requires three inputs : the initial architecture ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale