CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 69.
55. lappuse
... evaluate if a given processor or processor feature improves performance for one , some , or all of the programs in the benchmark suite . Compilers can also be designed and evaluated using benchmark suites as they execute on processor ...
... evaluate if a given processor or processor feature improves performance for one , some , or all of the programs in the benchmark suite . Compilers can also be designed and evaluated using benchmark suites as they execute on processor ...
56. lappuse
... evaluation of the chip will , in general , be more complex than for pure DA or pure CA designs . For example , CA might use a single benchmark runtime to evaluate the performance of a processor , while DA might use the number of gates ...
... evaluation of the chip will , in general , be more complex than for pure DA or pure CA designs . For example , CA might use a single benchmark runtime to evaluate the performance of a processor , while DA might use the number of gates ...
185. lappuse
... evaluate the performance indexes to be optimized for any mapping ) , and an Exploration en- gine ( which determines the next mapping to be evaluated ) . The inputs to the framework are : Architectural parameters : for example ...
... evaluate the performance indexes to be optimized for any mapping ) , and an Exploration en- gine ( which determines the next mapping to be evaluated ) . The inputs to the framework are : Architectural parameters : for example ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale