CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 61.
108. lappuse
... Energy Cost Overlay Algorithm Model Machine Program Trace Generation Static Allocation Algorithm Machine Program TotalEnergy ( SO ) TotalEnergy SA ) 10000 9000 8000 7000 + A 6000+ Energy Consumption J ) 5000+ 4000 3000+ 2000 + 1000 + ...
... Energy Cost Overlay Algorithm Model Machine Program Trace Generation Static Allocation Algorithm Machine Program TotalEnergy ( SO ) TotalEnergy SA ) 10000 9000 8000 7000 + A 6000+ Energy Consumption J ) 5000+ 4000 3000+ 2000 + 1000 + ...
109. lappuse
... Energy , Performance and Code Size comparison using SO vs. SA algorithm trend of energy consumption values remains the same for all the benchmarks . Consequently , a comparison of the two allocation al- gorithms is presented for a ...
... Energy , Performance and Code Size comparison using SO vs. SA algorithm trend of energy consumption values remains the same for all the benchmarks . Consequently , a comparison of the two allocation al- gorithms is presented for a ...
115. lappuse
... Energy Models To examine the energy model's effects , we apply different schemes on the task set under different energy settings . The task set has the same statistical performance requirement as that in Section 5.2 . Figure 3 shows the ...
... Energy Models To examine the energy model's effects , we apply different schemes on the task set under different energy settings . The task set has the same statistical performance requirement as that in Section 5.2 . Figure 3 shows the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale