CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 80.
72. lappuse
Panel Secure and Safety - Critical vs. Insecure , Non Safety - Critical Embedded Systems : Do they Require Completely Different Design Approaches ? Keynote Cellular Handset Technology System Requirements and Integration Trends Sven.
Panel Secure and Safety - Critical vs. Insecure , Non Safety - Critical Embedded Systems : Do they Require Completely Different Design Approaches ? Keynote Cellular Handset Technology System Requirements and Integration Trends Sven.
73. lappuse
... EMBEDDED SECURITY Security is crucial for many embedded systems ranging from smart cards , cell phones , to any embedded device which supports internet connectivity , software complexity , or extensibility [ 7 ] . Analogous to safety ...
... EMBEDDED SECURITY Security is crucial for many embedded systems ranging from smart cards , cell phones , to any embedded device which supports internet connectivity , software complexity , or extensibility [ 7 ] . Analogous to safety ...
110. lappuse
... Systems ] : Organization and Design - real - time systems and embedded sys- tems ; D.4.1 [ Operating Systems ] : Process Management — scheduling ; J.7 [ Computers in Other Systems ] : Real - time ; C.3 [ Special - Purpose and ...
... Systems ] : Organization and Design - real - time systems and embedded sys- tems ; D.4.1 [ Operating Systems ] : Process Management — scheduling ; J.7 [ Computers in Other Systems ] : Real - time ; C.3 [ Special - Purpose and ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale