CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 85.
6. lappuse
... embedded processors that use clustered execution units to deliver high levels of performance . However , delivering data to the execution resources in a timely manner re- mains a major problem that limits ILP . It is particularly ...
... embedded processors that use clustered execution units to deliver high levels of performance . However , delivering data to the execution resources in a timely manner re- mains a major problem that limits ILP . It is particularly ...
73. lappuse
... EMBEDDED SECURITY Security is crucial for many embedded systems ranging from smart cards , cell phones , to any embedded device which supports internet connectivity , software complexity , or extensibility [ 7 ] . Analogous to safety ...
... EMBEDDED SECURITY Security is crucial for many embedded systems ranging from smart cards , cell phones , to any embedded device which supports internet connectivity , software complexity , or extensibility [ 7 ] . Analogous to safety ...
224. lappuse
... Embedded JVM Environments G. Chen. ABSTRACT Future embedded and wireless devices will be increasingly powerful supporting many applications including one of the most crucial , security . Although many wireless and embedded devices offer ...
... Embedded JVM Environments G. Chen. ABSTRACT Future embedded and wireless devices will be increasingly powerful supporting many applications including one of the most crucial , security . Although many wireless and embedded devices offer ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale