CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 56.
56. lappuse
... elements that utilize conventional programmability of the CA approach , the I / O datasets introduce system - level timing demands from the DA approach , and the scenario programs schedule the application groupings . Figure 3 shows how ...
... elements that utilize conventional programmability of the CA approach , the I / O datasets introduce system - level timing demands from the DA approach , and the scenario programs schedule the application groupings . Figure 3 shows how ...
82. lappuse
... elements in the Generic Class Library are divided into four groups : • • • Data containers : elements of this group are containers parametric in the data type ( e.g. Memory , FIFO , Stack , etc. ) . Interfaces : elements of this group ...
... elements in the Generic Class Library are divided into four groups : • • • Data containers : elements of this group are containers parametric in the data type ( e.g. Memory , FIFO , Stack , etc. ) . Interfaces : elements of this group ...
251. lappuse
... elements on the same bus for further investigation . Although swapping more than two processing elements may yield better results , it incurs longer exploration time . Thus , as a trade - off , we allow swapping of only two processing ...
... elements on the same bus for further investigation . Although swapping more than two processing elements may yield better results , it incurs longer exploration time . Thus , as a trade - off , we allow swapping of only two processing ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale