CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 64.
48. lappuse
... distributed system object component ( DSOC ) message passing model , and a symmetrical multi - processing ( SMP ) model using shared memory . The MultiFlex tools map these models onto the StepNP multi - processor SoC platform , while ...
... distributed system object component ( DSOC ) message passing model , and a symmetrical multi - processing ( SMP ) model using shared memory . The MultiFlex tools map these models onto the StepNP multi - processor SoC platform , while ...
49. lappuse
... distributed systems development , but adapted and constrained for the SoC domain : Distributed System Object Component ( DSOC ) model . This model supports heterogeneous distributed computing , reminiscent of CORBA and Microsoft DCOM ...
... distributed systems development , but adapted and constrained for the SoC domain : Distributed System Object Component ( DSOC ) model . This model supports heterogeneous distributed computing , reminiscent of CORBA and Microsoft DCOM ...
176. lappuse
... distributed standing wave on the clock - wires across the whole chip [ 11 ] and travelling clock waves [ 13 ] . A good overview over different clocking methodologies can be found in [ 4 ] . In mesochronous clocking , the frequency is ...
... distributed standing wave on the clock - wires across the whole chip [ 11 ] and travelling clock waves [ 13 ] . A good overview over different clocking methodologies can be found in [ 4 ] . In mesochronous clocking , the frequency is ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale