CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 50.
120. lappuse
... devices , we have reduced the reconfiguration time of a Virtex - II device XC2V1000 from 8ms ( full / complete device reconfiguration ) to 1.4ms ( partial device reconfiguration ) , using a reconfiguration clock of 66MHz . 6.4 Tasks ...
... devices , we have reduced the reconfiguration time of a Virtex - II device XC2V1000 from 8ms ( full / complete device reconfiguration ) to 1.4ms ( partial device reconfiguration ) , using a reconfiguration clock of 66MHz . 6.4 Tasks ...
150. lappuse
... DEVICE WIDTH CALCULATION ( 26 ) As can be noted from the previous section , the analytical mod- els for leakage power in arrays depend on the device widths . Hence , for early estimation of leakage power , it is necessary to determine ...
... DEVICE WIDTH CALCULATION ( 26 ) As can be noted from the previous section , the analytical mod- els for leakage power in arrays depend on the device widths . Hence , for early estimation of leakage power , it is necessary to determine ...
151. lappuse
... Device Width Figure 6 : Plot Showing the Accuracy of Leakage Current Model for a NMOS Device that the maximum error in this model is 9 % and the average error is observed to be 2 % . mismatch in the calculated device widths and the actual ...
... Device Width Figure 6 : Plot Showing the Accuracy of Leakage Current Model for a NMOS Device that the maximum error in this model is 9 % and the average error is observed to be 2 % . mismatch in the calculated device widths and the actual ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale