CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 49.
85. lappuse
... developed code size ) depend exclusively from the fact that it has been necessary to modify the ATM Cell ADT as described in section 3.2 , while in [ 21 ] it has been directly taken from the Application Specific Library . Moreover , the ...
... developed code size ) depend exclusively from the fact that it has been necessary to modify the ATM Cell ADT as described in section 3.2 , while in [ 21 ] it has been directly taken from the Application Specific Library . Moreover , the ...
147. lappuse
... developed techniques for estimation of maximum leakage power in combinational logic based on simulation . Also ... develop an architectural model for sub - threshold and gate leakage that explicitly captures in temperature , voltage ...
... developed techniques for estimation of maximum leakage power in combinational logic based on simulation . Also ... develop an architectural model for sub - threshold and gate leakage that explicitly captures in temperature , voltage ...
159. lappuse
... developed . A case study using a JPEG decoder application is presented in Section 4. Section 5 concludes this paper with a summary . 2. RELATED WORK Hardware / software cosimulation has been studied around the world for more than a ...
... developed . A case study using a JPEG decoder application is presented in Section 4. Section 5 concludes this paper with a summary . 2. RELATED WORK Hardware / software cosimulation has been studied around the world for more than a ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale