CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 19.
15. lappuse
resentation depicting the dependency of instructions in an instruction trace , where nodes represent instructions , and directed edges represent dependency . A node has a type that corresponds to the type of instruction it represents ...
resentation depicting the dependency of instructions in an instruction trace , where nodes represent instructions , and directed edges represent dependency . A node has a type that corresponds to the type of instruction it represents ...
218. lappuse
... dependency on data and program ) compromise the security of the system . The technique flattens the current internally by ... dependencies is proposed . Measured and simulated current waveforms of cryptographic software are presented in ...
... dependency on data and program ) compromise the security of the system . The technique flattens the current internally by ... dependencies is proposed . Measured and simulated current waveforms of cryptographic software are presented in ...
219. lappuse
... dependencies and thus increase the security against simple power analysis attacks [ 7 ] . However , the current to data dependencies , and as a result the DPA attacks , are not efficiently supported by the software technique . Unlike ...
... dependencies and thus increase the security against simple power analysis attacks [ 7 ] . However , the current to data dependencies , and as a result the DPA attacks , are not efficiently supported by the software technique . Unlike ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale