CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 40.
10. lappuse
... delay product [ 3 ] . Both architecture and semiconductor process influence the energy delay product . Since the feature size of the process , X , has a large impact it is necessary to normalize designs to the same process for ...
... delay product [ 3 ] . Both architecture and semiconductor process influence the energy delay product . Since the feature size of the process , X , has a large impact it is necessary to normalize designs to the same process for ...
143. lappuse
... Delay ( J'S ) 100 60 00 40 20 20 16 86 8 Other 4 21 2 10 0 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M Cache Size ( bytes ) 2M 4M BM Contexts / PE Speech PES 16 8 Figure 2 : Fraction of L2 misses by data stream for a 4- processor , 4 ...
... Delay ( J'S ) 100 60 00 40 20 20 16 86 8 Other 4 21 2 10 0 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M Cache Size ( bytes ) 2M 4M BM Contexts / PE Speech PES 16 8 Figure 2 : Fraction of L2 misses by data stream for a 4- processor , 4 ...
174. lappuse
... delay of an edge . However , we cannot know its exact value due to the asynchronous communication protocol of an NoC . Moreover , the communication delay at a link is dependent on how many communication loads share the link . So , we ...
... delay of an edge . However , we cannot know its exact value due to the asynchronous communication protocol of an NoC . Moreover , the communication delay at a link is dependent on how many communication loads share the link . So , we ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale