CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 86.
20. lappuse
... defined or pre - defined components from a library , the designer invokes the operation extraction routine . At this point , the designer will see what operations the data path supports . If components are utilized in an unexpected way ...
... defined or pre - defined components from a library , the designer invokes the operation extraction routine . At this point , the designer will see what operations the data path supports . If components are utilized in an unexpected way ...
106. lappuse
... defined or modified but are always executed . Consequently , all basic blocks are assigned a USE refer- ence to the ... defined on every edge originating from a node with a DEF attribute . In contrast , the MOD or USE attribute is ...
... defined or modified but are always executed . Consequently , all basic blocks are assigned a USE refer- ence to the ... defined on every edge originating from a node with a DEF attribute . In contrast , the MOD or USE attribute is ...
196. lappuse
... defined in Table 1 . The processor pipeline divides the execution of an oper- ation into cycles . An otCycle is defined corresponding to each execution cycle of an operation . The OT is defined as an ordered list of otcycle . Thus the ...
... defined in Table 1 . The processor pipeline divides the execution of an oper- ation into cycles . An otCycle is defined corresponding to each execution cycle of an operation . The OT is defined as an ordered list of otcycle . Thus the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale