CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 64.
17. lappuse
... cost in number of cells . The system was synthesized to a cell library of 0.35 microns from AMI . The simulation results are shown in Table 2. The first col- umn gives the name of the application , the second and third the area cost of ...
... cost in number of cells . The system was synthesized to a cell library of 0.35 microns from AMI . The simulation results are shown in Table 2. The first col- umn gives the name of the application , the second and third the area cost of ...
64. lappuse
... cost of partial maps PM [ m , p ] and PM [ p + 1 , n ] , cost of new shared memories instan- tiated and cost of new links introduced . To illustrate , let us con- sider adjacent process_list of Figure 1 again . While combining partial ...
... cost of partial maps PM [ m , p ] and PM [ p + 1 , n ] , cost of new shared memories instan- tiated and cost of new links introduced . To illustrate , let us con- sider adjacent process_list of Figure 1 again . While combining partial ...
125. lappuse
... cost of a significant amount of hardware area . Given our view of SA as a sequence of moves each of which is blindly accepted , or probabilistically rejected depending upon its degree of suboptimality , we define a cost function on the ...
... cost of a significant amount of hardware area . Given our view of SA as a sequence of moves each of which is blindly accepted , or probabilistically rejected depending upon its degree of suboptimality , we define a cost function on the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale