CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 5.
142. lappuse
... coprocessor - Logical RF partition DRAM Chips ROM Chips XScale Processor Memory Controller PE DRAM ROM Controller Ctrl Speech Coprocessor Model PE Basic Model : LB - Memory Bus ( shared with XScale ) 64b PE 16b control / communication ...
... coprocessor - Logical RF partition DRAM Chips ROM Chips XScale Processor Memory Controller PE DRAM ROM Controller Ctrl Speech Coprocessor Model PE Basic Model : LB - Memory Bus ( shared with XScale ) 64b PE 16b control / communication ...
215. lappuse
... coprocessor . Likewise , the main processing part of the motion segmentation is described as an independent task , which is mapped onto a motion estimator ... coprocessor . 7.2.1 TTL Shell for the SI Coprocessor The TTL interface 215.
... coprocessor . Likewise , the main processing part of the motion segmentation is described as an independent task , which is mapped onto a motion estimator ... coprocessor . 7.2.1 TTL Shell for the SI Coprocessor The TTL interface 215.
216. lappuse
... coprocessor . See Figure 23. A DTL interface connects the shell to the communication interconnect . The request and acknowledge signals are used to handshake a TTL call from the coprocessor to the shell . The shell is able to handle ...
... coprocessor . See Figure 23. A DTL interface connects the shell to the communication interconnect . The request and acknowledge signals are used to handshake a TTL call from the coprocessor to the shell . The shell is able to handle ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale