CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 83.
20. lappuse
... constraints to equate connected ports and to assert each component's constraint literal ( e.g. inc , dec , mux , demux ) . We then find the set of satisfying solutions using an iterative SAT procedure , called FindMinimalOperations ...
... constraints to equate connected ports and to assert each component's constraint literal ( e.g. inc , dec , mux , demux ) . We then find the set of satisfying solutions using an iterative SAT procedure , called FindMinimalOperations ...
91. lappuse
... constraints are unsatisfiable , then the whole system is unsatisfiable since no typing context which contains mappings for the type variables in the sub - constraint will solve the original constraint . If all the sub - constraints are ...
... constraints are unsatisfiable , then the whole system is unsatisfiable since no typing context which contains mappings for the type variables in the sub - constraint will solve the original constraint . If all the sub - constraints are ...
107. lappuse
... constraints ( eqn . 7 , 8 and 9 , 10 ) are added to ensure a legal flow of liveness on merge and diverge nodes , re- spectively . More importantly , the constraints ensure an optimal spill code placement [ 8 ] . The following merge ...
... constraints ( eqn . 7 , 8 and 9 , 10 ) are added to ensure a legal flow of liveness on merge and diverge nodes , re- spectively . More importantly , the constraints ensure an optimal spill code placement [ 8 ] . The following merge ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale