CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 31.
116. lappuse
... configuration- aware data size partitioning approach . We propose a design methodology that adapts the architecture and used algorithms to the application requirements . The methodology has been proven to work on a real research ...
... configuration- aware data size partitioning approach . We propose a design methodology that adapts the architecture and used algorithms to the application requirements . The methodology has been proven to work on a real research ...
118. lappuse
... ( configuration ) replication . The output of this step is the modified task graph . The HW / SW synthesis is the process of implementing the tasks found in the application . The output of this process is a set of estimators . Typical ...
... ( configuration ) replication . The output of this step is the modified task graph . The HW / SW synthesis is the process of implementing the tasks found in the application . The output of this process is a set of estimators . Typical ...
120. lappuse
... configuration context in the device ( i.e. SRAM cells that store the device configuration bits ) . The CPU power consumption is shown in figure 9.b. , which in execution includes the power of the processor core [ 1 ] and the used on ...
... configuration context in the device ( i.e. SRAM cells that store the device configuration bits ) . The CPU power consumption is shown in figure 9.b. , which in execution includes the power of the processor core [ 1 ] and the used on ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale