CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 8.
56. lappuse
... compression , cyclic redundancy check ( CRC ) , MP3 decoding algorithm ( mad ) , rijndael encryption , adaptive pulse code modulation ( ADPCM ) which is used to compress voice data , and speech synthesis ( rsynth ) . WIRELESS NETWORK ...
... compression , cyclic redundancy check ( CRC ) , MP3 decoding algorithm ( mad ) , rijndael encryption , adaptive pulse code modulation ( ADPCM ) which is used to compress voice data , and speech synthesis ( rsynth ) . WIRELESS NETWORK ...
143. lappuse
... Compression We consider the potential benefit of maintaining compressed data on - chip , increasing the effective size of the L2 and thereby reducing memory demand . We evaluate the poten- tial for such an optimization by compressing ...
... Compression We consider the potential benefit of maintaining compressed data on - chip , increasing the effective size of the L2 and thereby reducing memory demand . We evaluate the poten- tial for such an optimization by compressing ...
145. lappuse
... Compress in Memory System Compression of static knowledge base data in the memory system can be done with minimum performance penalty . Main- taining compressed data is the L2 does not provide substantial performance benefits , though ...
... Compress in Memory System Compression of static knowledge base data in the memory system can be done with minimum performance penalty . Main- taining compressed data is the L2 does not provide substantial performance benefits , though ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale