CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 38.
42. lappuse
... complexity that permits to tackle complex designs in a reasonable time . Categories and Subject Descriptors B.5 [ RTL Implementation ] : Design Aids General Terms Design , Algorithms , Theory , Experimentation Keywords Memory aware ...
... complexity that permits to tackle complex designs in a reasonable time . Categories and Subject Descriptors B.5 [ RTL Implementation ] : Design Aids General Terms Design , Algorithms , Theory , Experimentation Keywords Memory aware ...
72. lappuse
... complexity while at the same time ensure safety and security ? Will new design approaches be required ? Or can ... complexities in designing a safety - critical system , specifically the future automobile . Section 3 details security ...
... complexity while at the same time ensure safety and security ? Will new design approaches be required ? Or can ... complexities in designing a safety - critical system , specifically the future automobile . Section 3 details security ...
236. lappuse
... complexity , on communi- cation architecture power . Based on our analyses , we evaluate different tech- niques for reducing the power consumed by the on - chip communication ar- chitecture , and compare their effectiveness in achieving ...
... complexity , on communi- cation architecture power . Based on our analyses , we evaluate different tech- niques for reducing the power consumed by the on - chip communication ar- chitecture , and compare their effectiveness in achieving ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale