CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 46.
9. lappuse
... complex to be handled by the address generator , the lower 2x1 mux selects an address that is computed by an ALU . To handle vectors and ALU generated addresses with one or zero loop vari- ables respectively , the loop unit has a ...
... complex to be handled by the address generator , the lower 2x1 mux selects an address that is computed by an ALU . To handle vectors and ALU generated addresses with one or zero loop vari- ables respectively , the loop unit has a ...
75. lappuse
... complex systems . The design and verification of complex systems is already a particularly perilous undertaking . Those who dare must withstand great pressures from escalating design costs and ever shortening design times . Along the ...
... complex systems . The design and verification of complex systems is already a particularly perilous undertaking . Those who dare must withstand great pressures from escalating design costs and ever shortening design times . Along the ...
236. lappuse
... complex System - on - chips ( SoCs ) fabricated in nanometer technologies , the system - level on - chip communication architecture is emerging as a signif- icant source of power consumption . Managing and optimizing this important ...
... complex System - on - chips ( SoCs ) fabricated in nanometer technologies , the system - level on - chip communication architecture is emerging as a signif- icant source of power consumption . Managing and optimizing this important ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale