CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 64.
82. lappuse
... Compiler ) or behavioral ( in this case it is given to SystemC Compiler ) . The abstraction level depends mostly on the adopted style for writing the SystemC - Plus model . The two SystemC - Plus libraries are used as design support in ...
... Compiler ) or behavioral ( in this case it is given to SystemC Compiler ) . The abstraction level depends mostly on the adopted style for writing the SystemC - Plus model . The two SystemC - Plus libraries are used as design support in ...
98. lappuse
Compiler - Directed Code Restructuring for Reducing Data TLB Energy I. Kadayif Dept. of Computer Engineering Canakkale Onsekiz Mart Univ . , TR ... Compiling and Scheduling Compiler-Directed Code Restructuring for Reducing Data TLB Energy.
Compiler - Directed Code Restructuring for Reducing Data TLB Energy I. Kadayif Dept. of Computer Engineering Canakkale Onsekiz Mart Univ . , TR ... Compiling and Scheduling Compiler-Directed Code Restructuring for Reducing Data TLB Energy.
99. lappuse
where f ( ) is not a compiler - analyzable function . In this case , the compiler restructures the computation around U1 using a loop transformation called strip - mining [ 17 ] : for s : 1 , N , P load translation for U1 [ s ] to TR ...
where f ( ) is not a compiler - analyzable function . In this case , the compiler restructures the computation around U1 using a loop transformation called strip - mining [ 17 ] : for s : 1 , N , P load translation for U1 [ s ] to TR ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale