CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 68.
121. lappuse
... compared to the software solution . We can also see that dynamic reconfiguration increases the energy consumption when compared to the HW / SW partitioning despite of its improvements in performance . Finally , in both figures we can ...
... compared to the software solution . We can also see that dynamic reconfiguration increases the energy consumption when compared to the HW / SW partitioning despite of its improvements in performance . Finally , in both figures we can ...
175. lappuse
... compared with the random mapping and XY - routing technique . The GA- based technique reduced the energy consumption by 28 % on av- erage , compared with the BB technique . We also experimented with the task graph of the real ...
... compared with the random mapping and XY - routing technique . The GA- based technique reduced the energy consumption by 28 % on av- erage , compared with the BB technique . We also experimented with the task graph of the real ...
234. lappuse
... compared to not using checksums ( see the y - axis on the left ) . Figure 3 : Error consumption behavior of different benchmarks . Left : CSOBJ . Right : CSFLD . Note that the NC class dominates the behavior with both the schemes . The ...
... compared to not using checksums ( see the y - axis on the left ) . Figure 3 : Error consumption behavior of different benchmarks . Left : CSOBJ . Right : CSFLD . Note that the NC class dominates the behavior with both the schemes . The ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale