CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 77.
66. lappuse
... communication architectures . A major challenge in modeling the communication architecture is managing the concurrency at multiple levels : at the operation level , multiple communication operations may be active at any time ; at the ...
... communication architectures . A major challenge in modeling the communication architecture is managing the concurrency at multiple levels : at the operation level , multiple communication operations may be active at any time ; at the ...
174. lappuse
... communication protocol of an NoC . Moreover , the communication delay at a link is dependent on how many communication loads share the link . So , we use the worst - case communication delay of each edge to satisfy the hard real - time ...
... communication protocol of an NoC . Moreover , the communication delay at a link is dependent on how many communication loads share the link . So , we use the worst - case communication delay of each edge to satisfy the hard real - time ...
236. lappuse
... communication ar- chitectures ( e.g. , low - swing buses , bus encoding , etc ) . While effective , they only address a limited part of communication architecture power consump- tion . A state - of - the - art communication architecture ...
... communication ar- chitectures ( e.g. , low - swing buses , bus encoding , etc ) . While effective , they only address a limited part of communication architecture power consump- tion . A state - of - the - art communication architecture ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale