CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 39.
98. lappuse
... circuit and architectural techniques . A recent software - based technique for data TLBS has considered the possibility of storing the frequently used virtual - to - physical address translations in a set of translation registers ( TRS ) ...
... circuit and architectural techniques . A recent software - based technique for data TLBS has considered the possibility of storing the frequently used virtual - to - physical address translations in a set of translation registers ( TRS ) ...
147. lappuse
... circuit , write column circuit , read control and write control circuit . We consider the typical implementation styles of these sub - blocks and develop leakage power models for each sub - block and for each of its operational phase ...
... circuit , write column circuit , read control and write control circuit . We consider the typical implementation styles of these sub - blocks and develop leakage power models for each sub - block and for each of its operational phase ...
150. lappuse
the circuit output drivers . This observation is not completely un- expected because the size of most logic gates in all these control circuits is driven by the size of the output drivers . The additional logic that these circuits may ...
the circuit output drivers . This observation is not completely un- expected because the size of most logic gates in all these control circuits is driven by the size of the output drivers . The additional logic that these circuits may ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale