CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 81.
54. lappuse
... chip . The design of other programmable single chip computers has enjoyed an era where the design trade - offs could be captured in simulators such as SimpleScalar and performance could be evaluated to the SPEC benchmarks . Motivated by ...
... chip . The design of other programmable single chip computers has enjoyed an era where the design trade - offs could be captured in simulators such as SimpleScalar and performance could be evaluated to the SPEC benchmarks . Motivated by ...
170. lappuse
... chip , Real - time systems , Low - power de- sign 1. INTRODUCTION Networks - on - Chip ( NoC ) have recently been proposed as a prac- tical development platform for systems - on - chip ( SoC ) products [ 1 , 3 ] . NoCs are especially ...
... chip , Real - time systems , Low - power de- sign 1. INTRODUCTION Networks - on - Chip ( NoC ) have recently been proposed as a prac- tical development platform for systems - on - chip ( SoC ) products [ 1 , 3 ] . NoCs are especially ...
236. lappuse
... chips ( SoCs ) fabricated in nanometer technologies , the system - level on - chip communication architecture is emerging as a signif- icant source of power consumption . Managing and optimizing this important component of SoC power ...
... chips ( SoCs ) fabricated in nanometer technologies , the system - level on - chip communication architecture is emerging as a signif- icant source of power consumption . Managing and optimizing this important component of SoC power ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale