CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 25.
211. lappuse
... channel . If the IQ task and the IZZ task need to execute concurrently , then the channel must be able to contain two blocks , i.e. , 128 pixels . The load function ( Figure 9 , Line 07 ) and the store function ( Figure 8 , Line 09 ) ...
... channel . If the IQ task and the IZZ task need to execute concurrently , then the channel must be able to contain two blocks , i.e. , 128 pixels . The load function ( Figure 9 , Line 07 ) and the store function ( Figure 8 , Line 09 ) ...
213. lappuse
... Channel Binding The last phase of source code transformation is the link to existing compilers and synthesizers in order to map the individual tasks to hardware and software . To this end , programmers specify a binding of tasks to ...
... Channel Binding The last phase of source code transformation is the link to existing compilers and synthesizers in order to map the individual tasks to hardware and software . To this end , programmers specify a binding of tasks to ...
216. lappuse
... channel implementation consists of two parts , the channel buffer and the channel administration . In the SI core the channel buffers are always located in main ( on - chip ) memory . The channel administration can be placed both in the ...
... channel implementation consists of two parts , the channel buffer and the channel administration . In the SI core the channel buffers are always located in main ( on - chip ) memory . The channel administration can be placed both in the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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