CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 39.
110. lappuse
... called Energy - efficient Utility Accrual Algorithm ( or EUA ) , for battery - powered , embed- ded real - time ... called Utility Accrual ( or UA ) criteria , and sequencing ( scheduling , dispatching ) algorithms that consider UA ...
... called Energy - efficient Utility Accrual Algorithm ( or EUA ) , for battery - powered , embed- ded real - time ... called Utility Accrual ( or UA ) criteria , and sequencing ( scheduling , dispatching ) algorithms that consider UA ...
220. lappuse
... called FLATTENO two current measurements are performed . Measurement 1 : This measurement determines the peak current value Im and the program execution time T1 of the original maxl unaltered program . Measurement 2 : This measurement ...
... called FLATTENO two current measurements are performed . Measurement 1 : This measurement determines the peak current value Im and the program execution time T1 of the original maxl unaltered program . Measurement 2 : This measurement ...
221. lappuse
... called FLATTENi was derived for the SC140 processor ( See Table 1 ) . The FLATTENi current equivalence rules ... called PAAR architecutre , is composed of 2 modules : feedback current flattening module called FCFM and the pipeline ...
... called FLATTENi was derived for the SC140 processor ( See Table 1 ) . The FLATTENi current equivalence rules ... called PAAR architecutre , is composed of 2 modules : feedback current flattening module called FCFM and the pipeline ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale