CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 38.
142. lappuse
... cache organization which affect the per- formance / energy tradeoff , rather than how specific cache architectures affect program performance . Consideration of effects such as line size , associativity , and cache replacement policy ...
... cache organization which affect the per- formance / energy tradeoff , rather than how specific cache architectures affect program performance . Consideration of effects such as line size , associativity , and cache replacement policy ...
143. lappuse
... cache to back up all L1 caches leads to further dramatic reductions in bandwidth demand and corresponding perfor- mance improvement . The overall analysis here is best pre- sented by Figure 2 , which depicts the percent of L2 misses at ...
... cache to back up all L1 caches leads to further dramatic reductions in bandwidth demand and corresponding perfor- mance improvement . The overall analysis here is best pre- sented by Figure 2 , which depicts the percent of L2 misses at ...
144. lappuse
... cache with SDRAM memory over those with DDR memory and no L2 cache . the memory system . We evaluate direct bandwidth improve- ment by moving to a DDR based system , and shifting of references through stream partitioning and use of ...
... cache with SDRAM memory over those with DDR memory and no L2 cache . the memory system . We evaluate direct bandwidth improve- ment by moving to a DDR based system , and shifting of references through stream partitioning and use of ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale