CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 41.
52. lappuse
buffer content . We assume in the following that both the SPI segment size and buffer size are 64 bytes . 8.2 DSOC Model A DSOC model of the traffic manager application is depicted in Figure 3 a ) . This model is composed of the ...
buffer content . We assume in the following that both the SPI segment size and buffer size are 64 bytes . 8.2 DSOC Model A DSOC model of the traffic manager application is depicted in Figure 3 a ) . This model is composed of the ...
131. lappuse
in the set of schedulers for which no buffer overflows and the playout buffer does not underflow . The playout buffer underflow constraint is to ensure that the output quality of the audio / video stream , as specified by the function C ...
in the set of schedulers for which no buffer overflows and the playout buffer does not underflow . The playout buffer underflow constraint is to ensure that the output quality of the audio / video stream , as specified by the function C ...
133. lappuse
... buffer underflows ( white cells ) . the possibility of fast design space exploration of hardware- software architectures of media processing platforms . Stan- dard methods for worst / best - case analysis from the real- P2 [ number of ...
... buffer underflows ( white cells ) . the possibility of fast design space exploration of hardware- software architectures of media processing platforms . Stan- dard methods for worst / best - case analysis from the real- P2 [ number of ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale