CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 64.
26. lappuse
... block has its local controller and there is no need of complicated central controller design . ( Figure 4 ( c ) ) A hardware block detects when it can be invoked by exchanging control signals with its neighbor based on a certain hand ...
... block has its local controller and there is no need of complicated central controller design . ( Figure 4 ( c ) ) A hardware block detects when it can be invoked by exchanging control signals with its neighbor based on a certain hand ...
28. lappuse
... blocks A , B and C are 30 , 20 and 80 time units respectively , while the execution time of node D is unknown ; the timing of done signal for block D varies at run - time . RCV A B Type A combinational logic с D SND Type B single ...
... blocks A , B and C are 30 , 20 and 80 time units respectively , while the execution time of node D is unknown ; the timing of done signal for block D varies at run - time . RCV A B Type A combinational logic с D SND Type B single ...
251. lappuse
... block fb . The criticality Cfb , ) of the function block fb , is the sum of the schedule length of function blocks on the longest execution path of those that can be executed only after fb ,. The bandwidth and the criticality of a function ...
... block fb . The criticality Cfb , ) of the function block fb , is the sum of the schedule length of function blocks on the longest execution path of those that can be executed only after fb ,. The bandwidth and the criticality of a function ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale