CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 56.
42. lappuse
... behavioral synthesis . We formalize the memory mapping as a set of constraints for the synthesis , and defined a ... behavior and number of control step are managed in function of the scheduling mode [ 5 ] . In practice , the number ...
... behavioral synthesis . We formalize the memory mapping as a set of constraints for the synthesis , and defined a ... behavior and number of control step are managed in function of the scheduling mode [ 5 ] . In practice , the number ...
111. lappuse
... behavior includ- ing application - defined , probabilistic , lower bounds on individual activity utility ; ( 2 ) provide assurances on system - level timeliness behavior including lower bound on the sum of activities ' attained ...
... behavior includ- ing application - defined , probabilistic , lower bounds on individual activity utility ; ( 2 ) provide assurances on system - level timeliness behavior including lower bound on the sum of activities ' attained ...
234. lappuse
... behavior of different benchmarks . Left : CSOBJ . Right : CSFLD . Note that the NC class dominates the behavior with both the schemes . The average contribution of NC in CSOBJ and CSFLD cases is 67.7 % and 84.7 % , respectively . Figure ...
... behavior of different benchmarks . Left : CSOBJ . Right : CSFLD . Note that the NC class dominates the behavior with both the schemes . The average contribution of NC in CSOBJ and CSFLD cases is 67.7 % and 84.7 % , respectively . Figure ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale