CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 49.
109. lappuse
... average reduction of 43 % . The application on average requires 21 % less CPU cycles for execution . The comparison of SO and SA algorithms across all benchmarks are presented in figure 8. The normalized energy values , the ex- ecution ...
... average reduction of 43 % . The application on average requires 21 % less CPU cycles for execution . The comparison of SO and SA algorithms across all benchmarks are presented in figure 8. The normalized energy values , the ex- ecution ...
180. lappuse
... average of these two will be the value of a single peak value . In fact , as long as the number of different clock phases across the NoC are even ( M = 2,4,6 , ... ) and equally spread across the clock period ( sum of all Ao along clock ...
... average of these two will be the value of a single peak value . In fact , as long as the number of different clock phases across the NoC are even ( M = 2,4,6 , ... ) and equally spread across the clock period ( sum of all Ao along clock ...
181. lappuse
... Average latency ( ns ) a , scheme 1 fixed b . scheme 2 M - 1 c . scheme 3 M = 2 d . scheme 3 M = 4 , scheme 3 M - 7 0 10 20 30 40 Transmission rate ( % ) 50 60 Figure 8 : Average latency in a 4 × 4 mesh with different trans- mission ...
... Average latency ( ns ) a , scheme 1 fixed b . scheme 2 M - 1 c . scheme 3 M = 2 d . scheme 3 M = 4 , scheme 3 M - 7 0 10 20 30 40 Transmission rate ( % ) 50 60 Figure 8 : Average latency in a 4 × 4 mesh with different trans- mission ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale