CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 32.
174. lappuse
... Assignment For the link speed assignment , we have used a similar idea to the voltage and clock speed selection algorithm proposed by Schmitz and Al - Hashimi [ 10 ] . Their algorithm first estimates the slack time of each task ...
... Assignment For the link speed assignment , we have used a similar idea to the voltage and clock speed selection algorithm proposed by Schmitz and Al - Hashimi [ 10 ] . Their algorithm first estimates the slack time of each task ...
191. lappuse
... assignment freedom because it affects most accesses ( line 9 : numera- tor ) , but the smallest impact on the performance ( line 9 : denominator ) . The edge weight heavily depends on which operations are executed in parallel and thus ...
... assignment freedom because it affects most accesses ( line 9 : numera- tor ) , but the smallest impact on the performance ( line 9 : denominator ) . The edge weight heavily depends on which operations are executed in parallel and thus ...
251. lappuse
... the heuristic technique for priority assignments : we compared the efficiency of the proposed priority assignment heuristic with the exhaustive assignment case for the architecture candidates during the exploration 251.
... the heuristic technique for priority assignments : we compared the efficiency of the proposed priority assignment heuristic with the exhaustive assignment case for the architecture candidates during the exploration 251.
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale