CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 85.
26. lappuse
... approach . Thus , the proposed approach ( b ) Figure 5 : Commonly used hardware architectures with ( a ) one 1 - D DCT resource and ( b ) four resources 3. PROPOSED HARDWARE SYNTHESIS TECHNIQUE Recall that the schedule information is ...
... approach . Thus , the proposed approach ( b ) Figure 5 : Commonly used hardware architectures with ( a ) one 1 - D DCT resource and ( b ) four resources 3. PROPOSED HARDWARE SYNTHESIS TECHNIQUE Recall that the schedule information is ...
60. lappuse
... approach for automatic synthesis of System on Chip ( SoC ) multiprocessor architectures for applications expressed as process networks . Our approach is targeted towards design space exploration ( DSE ) and thus the speed of synthesis ...
... approach for automatic synthesis of System on Chip ( SoC ) multiprocessor architectures for applications expressed as process networks . Our approach is targeted towards design space exploration ( DSE ) and thus the speed of synthesis ...
65. lappuse
... approach suitable to be used in a design space exploration framework . Number of processes 10 20 Number of queues 19 57 30 60 Time taken in Sol . < 1 sec < 1 sec < 1 sec Number of instantiated processors 3 Number of shared memories I 5 ...
... approach suitable to be used in a design space exploration framework . Number of processes 10 20 Number of queues 19 57 30 60 Time taken in Sol . < 1 sec < 1 sec < 1 sec Number of instantiated processors 3 Number of shared memories I 5 ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale