CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 87.
56. lappuse
... application groupings are formed from application elements that utilize conventional programmability of the CA approach , the I / O datasets introduce system - level timing demands from the DA approach , and the scenario programs ...
... application groupings are formed from application elements that utilize conventional programmability of the CA approach , the I / O datasets introduce system - level timing demands from the DA approach , and the scenario programs ...
57. lappuse
... application groupings as applications compete for system resources . Thus , the size , values and arrival rates of I / O datasets are an important part of scenarios . 3.3 Scenario Programs Even in this relatively straightforward cell ...
... application groupings as applications compete for system resources . Thus , the size , values and arrival rates of I / O datasets are an important part of scenarios . 3.3 Scenario Programs Even in this relatively straightforward cell ...
58. lappuse
... application mappings are listed in Table 1. Notice that the read_e - mail application , which includes a floating point rsynth benchmark , is placed onto P1 . Also , MP3 decoding is a more computationally intensive application , and was ...
... application mappings are listed in Table 1. Notice that the read_e - mail application , which includes a floating point rsynth benchmark , is placed onto P1 . Also , MP3 decoding is a more computationally intensive application , and was ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale