CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 72.
93. lappuse
... analysis shown in Figure 2 . Use Case Analysis Use Case Diagram Use Case Description Class Diagram Static Analysis The static analysis is used for extracting data objects and control objects from the specification . Data objects can be ...
... analysis shown in Figure 2 . Use Case Analysis Use Case Diagram Use Case Description Class Diagram Static Analysis The static analysis is used for extracting data objects and control objects from the specification . Data objects can be ...
218. lappuse
... analysis attacks , hardware architecture . 1. INTRODUCTION Due to recent increase in security usage , improved software and hardware countermeasures against power analysis attacks are needed . Current and power consumption dependency on ...
... analysis attacks , hardware architecture . 1. INTRODUCTION Due to recent increase in security usage , improved software and hardware countermeasures against power analysis attacks are needed . Current and power consumption dependency on ...
223. lappuse
... analysis attack resistant ) architecture that implements the software principles of the current flattening technique in hardware was developed . Theoretically the PAAR architecture could overcome all power analysis attacks without ...
... analysis attack resistant ) architecture that implements the software principles of the current flattening technique in hardware was developed . Theoretically the PAAR architecture could overcome all power analysis attacks without ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale