CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 75.
81. lappuse
... allows the exploitation of the key features of the O0 paradigm ( i.e. information hiding , inheritance , and polymorphism ) at the behavioral level of description while guaranteeing synthesizability . In this context , the goal of this ...
... allows the exploitation of the key features of the O0 paradigm ( i.e. information hiding , inheritance , and polymorphism ) at the behavioral level of description while guaranteeing synthesizability . In this context , the goal of this ...
122. lappuse
... allowing call graphs with thousands of vertices to be pro- cessed in less than a second , and 2 ) we devise a new cost function for SA that allows frequent discovery of better partitioning solu- tions by searching spaces overlooked by ...
... allowing call graphs with thousands of vertices to be pro- cessed in less than a second , and 2 ) we devise a new cost function for SA that allows frequent discovery of better partitioning solu- tions by searching spaces overlooked by ...
207. lappuse
... allow a broad range of platform implementations , including different multiprocessor architectures . For example , both shared memory and message- passing architectures should be supported . Further , the abstraction allows critical ...
... allow a broad range of platform implementations , including different multiprocessor architectures . For example , both shared memory and message- passing architectures should be supported . Further , the abstraction allows critical ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale