CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 8.
49. lappuse
... adapted and constrained for the SoC domain : Distributed System Object Component ( DSOC ) model . This model supports heterogeneous distributed computing , reminiscent of CORBA and Microsoft DCOM distributed component object models . It ...
... adapted and constrained for the SoC domain : Distributed System Object Component ( DSOC ) model . This model supports heterogeneous distributed computing , reminiscent of CORBA and Microsoft DCOM distributed component object models . It ...
123. lappuse
... adaptation for our problem . In [ 4 ] , the dynamic weighting tech- nique was applied towards the secondary objective of minimizing HW area once the primary objective , the timing constraint , was al- most satisfied . We however , apply ...
... adaptation for our problem . In [ 4 ] , the dynamic weighting tech- nique was applied towards the secondary objective of minimizing HW area once the primary objective , the timing constraint , was al- most satisfied . We however , apply ...
176. lappuse
... adapting the switching policy in the switches to prefer data to use the motorways , we show that the latency within the network is reduced with up to 40 % compared to a synchronous reference case . The phase difference between the ...
... adapting the switching policy in the switches to prefer data to use the motorways , we show that the latency within the network is reduced with up to 40 % compared to a synchronous reference case . The phase difference between the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale