CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 49.
43. lappuse
... achieve these transfers . The def- inition of the memory architecture will be performed in the first step of the overall design flow . To achieve this task , ad- vanced compilers such as Rice HPF compiler , Illinois Polaris or Stanford ...
... achieve these transfers . The def- inition of the memory architecture will be performed in the first step of the overall design flow . To achieve this task , ad- vanced compilers such as Rice HPF compiler , Illinois Polaris or Stanford ...
220. lappuse
... achieve a desired flattening effect . The following subsection presents an empirical methodology that can solve some of these problems . 3.1 Empirical Method for Generating Code Transformation Applicable to ICFT The method developed in ...
... achieve a desired flattening effect . The following subsection presents an empirical methodology that can solve some of these problems . 3.1 Empirical Method for Generating Code Transformation Applicable to ICFT The method developed in ...
241. lappuse
... achieve power savings , it may result in increased delay on the bus lines , due to the additional control logic ... achieved . This is due to 70 % savings in bus line power , and 11 % savings in interface power . The impact on interface ...
... achieve power savings , it may result in increased delay on the bus lines , due to the additional control logic ... achieved . This is due to 70 % savings in bus line power , and 11 % savings in interface power . The impact on interface ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale